A crucial component of integrated circuits is the wiring or metallization layer that interconnects the individual circuits. Conventional metal deposition techniques included physical vapor deposition, e.g., sputtering and evaporation, and chemical vapor deposition techniques. More recently, integrated circuit and equipment manufacturers developed electroplating (i.e., electrochemical deposition) techniques to deposit primary conductor films on semiconductor substrates.
Copper and copper alloys are widely used in the field of semiconductor fabrication as conducting materials. As a conductor, copper is often preferred to other metals, such as aluminum, due to its high electrical conductivity and good electromigration resistance properties. Because of these advantages, copper-filled lines and vias are now ubiquitously seen as conducting paths connecting elements of semiconductor devices, such as in integrated circuits. The transition from aluminum to copper wiring layers resulted in changes in process architecture towards damascene and dual damascene architecture, as well as new process technologies. Copper or other conductive metal layers are typically deposited on a dielectric layer. The dielectric layer typically contains openings, or feature cavities, (e.g., vias and trenches) that are filled with the conductive material to provide a path through the dielectric layer to previously deposited layers and to circuit devices. After the conductive material is removed from exposed field areas outside the feature cavities, only conductive material filling the feature cavities remains in the dielectric layer.
A typical damascene or dual damascene process flow scheme for fabricating copper interconnects, such as copper lines and vias, typically includes: forming a trench pattern on a layer dielectric layer using an etch-resistant photoresist; etching a trench pattern; removing the photoresist; forming a via pattern on a dielectric material using etch resistant photoresist; etching vias; removing resist; depositing a barrier (e.g., tantalum, tantalum nitride, and combination of these) and a copper seed layer (e.g. using plasma vapor deposition, PVD); electroplating copper to fill the etched feature cavities; and removing (e.g., polishing) copper and barrier off the wafer face leaving copper-filled electrically isolated interconnect circuitry.
As the number of levels in an interconnect technology is increased, the stacking of additional layers produces more rugged and complex topography. Compounding this problem, electroplating bath additives are now commonly utilized to promote rapid “bottom-up” filling of high aspect-ratio features in damascene copper electroplating processes to ensure complete void-free metal fill of high aspect ratio features (features deeper than they are wide). Baths with good “bottom-up” filling characteristics fill high aspect ratio features more rapidly and without creating void or seam when compared to baths with less effective combinations of such additives. In some cases (e.g., plating baths with superior bottom-up filling characteristics and little or no leveling additives), plating continues at an accelerated rate after completing the small-feature filling stage. When many high-aspect ratio features are located in close proximity, the high degree of adsorbed accelerator originally associated with the large surface area of that region remains after the features have filled. Hence, growth continues at an accelerated rate beyond the point of filled features, and into the period where metal between the features has merged. When this happens, a macroscopic raised area (series of thicker metallized bumps or a raised plateau) forms over the entire region above underlying high aspect ratio features. This bump formation is also termed “feature overplating” or “momentum plating”.
The use of advanced “bottom-up” electrofilling techniques with wafers having both low and high aspect-ratio features has created a problem of deposited metal surfaces with a wide range of topography, that is, topography containing a large range of height and width variations in both recessed and raised areas. Commonly, features vary in width by two to three orders of magnitude on a single layer. As a specific example, a 0.5 μm-deep (thick dielectric) level can have feature widths of from 0.1 μm to 100 μm. Therefore, while electroplating is the preferred method of metallization, various aspects of improved plating regimens create challenging topography for subsequent planarization.
A principal objective of damascene circuit interconnect fabrication is to create metal isolated by and embedded in a dielectric medium. Modern copper electroplating for damascene processes proceeds by a “bottom up” fill mechanism that preferentially fills high-aspect-ratio features such as deep trenches and vias on a wafer surface. The preferential filling of recessed features requires careful control of process conditions. U.S. Pat. No. 6,946,065, titled “Process for Electroplating Metal into Microscopic Recessed Features”, issued Sep. 20, 2005 to Mayer et. al., which is hereby incorporated by reference for all purposes, teaches techniques for reducing or avoiding the formation of seams and/or voids when electroplating the interior regions of microscopic recessed features. For the most part, prior art processes do not preferentially fill and planarize low-aspect-ratio features and, therefore, they require significant excess metal deposition (“overburden.”) Overburden is the additional copper deposited on the substrate to ensure that all low-aspect-ratio features are completely filled (essentially in an isotropic fashion) to the plane of a base layer, that is, to the plane of the isolating dielectric surface (the “field”). Since the preferential “bottom-up” filling generally does not occur in low-aspect-ratio features, the surface of the overburden above low-aspect-ratio features typically follows the contours of the underlying low-aspect-ratio features. In most cases, the overburden on field regions is slightly thicker than the thickness of the damascene dielectric layer, typically on the order of 1.2 times the depth of the deepest feature. So, for example, a damascene structure that has 0.5 micrometers (μm) deep features typically requires an overburden of at least approximately 0.7 μm to 0.8 μm.
The goal of damascene fabrication operations is to isolate finally the individual lines within the feature cavities of the dielectric layer. Since the filling of low-aspect-ratio features is largely isotropic, plating leads to very little if any reduction in the overall topography of the surface. The step change in plated topography is essentially identical to the initial patterned cavity (recess) depth in the dielectric medium. Note that if metal overburden were isotropically removed after filling of low-aspect-ratio feature cavities, then these low-aspect-ratio features would loose metal below the plane of the dielectric (i.e., below the field plane) before the metal over high-aspect-ratio lines and the field-area metal were removed. Various approaches and techniques of plating, planarization and polishing have been developed in the prior art with the goal that metal still completely fills these low-aspect-ratio features after overburden has been removed and the individual metal lines have been isolated. These approaches and techniques generally require overburden.
A problem sometimes arises during processing of surfaces in which a large number of low aspect-ratio (larger width than depth) features exist. Wide interconnect lines (trenches cut in a dielectric layer for a damascene process) and contact/bond pads often have low aspect ratios. Low-aspect-ratio features generally require the plating of an overburden layer slightly thicker than the thickness of the damascene layer so that the feature is completely filled after planarization. The metal fill profile above these features exhibits large recesses having profiles that resemble the original low aspect-ratio feature. The metal processes used to deposit the metal, which are substantially conformal over such low aspect-ratio features, are often not continued to a point that would geometrically “close” such recesses, because to do so would require depositing a very thick metal layer. Depositing a thick metal layer would be uneconomical due to necessary removal of the large excess of metal at a later stage. Conventional electropolishing techniques can planarize a surface in which the recessed feature to be planarized is no more than perhaps three times as wide as it is deep. For features wider than these, the rate of removal is essentially uniform everywhere. When the metal layer is electropolished to the dielectric surface, recesses over low-aspect-ratio features are propagated and expanded to produce recesses that span the width of these features, leaving effectively little or no metal in the metal pad regions. This is an unacceptable result.
A through-silicon via (TSV) is a vertical electrical connection passing completely through a silicon wafer or a die. TSV technology may be used in 3D packages and 3D integrated circuits, sometimes collectively referred to as 3D stacking. For example, a 3D package may contain two or more integrated circuits (ICs) stacked vertically so that they occupy less space. Traditionally, stacked ICs are interconnected together along their edges using wires, but such wiring can have a limited bandwidth, and increases the stack's dimensions and usually requires extra layers between the ICs. TSVs provide connections through the body of the ICs leading to smaller stacks. Similarly, a 3D single IC may be built by stacking several silicon wafers and interconnecting them vertically. Such stacks behave as a single device and can have shorter critical electrical paths leading to faster operation. Typically, TSV holes may be between about 5 to 400 microns deep (often between about 25 to 150 microns deep). The diameter or width dimension of TSV holes may vary between about 1 to 100 microns (more typically between about 5 to 25 microns). The TSV holes typically have a high aspect ratio, which is defined as the ratio of the TSV-hole depth to the TSV-hole diameter (usually at the opening). In certain applications, the TSV hole aspect ratio may vary between about 3:1 to 10:1. TSV size also depends on which stage of the overall 3D stacking process includes TSV formation. The filling of TSV holes using electroplating techniques often results in the deposition of thick non-planar copper layers characterized by depressions, or “dimples”, or by mounds or protrusion, located above TSV feature cavities.
Similar problems may arise from chemical (nonelectrolytic) wet etching of metal from a substrate surface. U.S. Pat. No. 5,486,234, issued Jan. 23, 1996, to Controlini et al., which is hereby incorporated by reference, teaches a method of spin-spray wet etching. To be of greatest utility, wet etching should generally proceed isotropically; that is, there is no selection between etching of metal from peaks and valleys of the substrate surface and etching occurs over the surface at substantially the same rate everywhere. In some circumstances, if chemical wet etching were conducted long enough to remove substantially the metal over field areas and above “overplated” high-aspect-ratio features of a nonplanar substrate, then excessive over-etching of metal and generation of recesses in low-aspect-ratio features would result.
There exists, therefore, a need for improved technology for planarizing conductive layers embedded in dielectric substrates having various feature sizes, particularly having both very narrow (submicron) and very wide (on the order of 100 μm) feature widths. Similarly, there exists a need in the semiconductor industry for planarizing thin metal films and fine metal interconnect lines inlaid on a patterned substrate that includes dielectric and barrier layer materials. There is also a need for removing thick metal layers from semiconductor substrates; for example, copper layers resulting from TSV filling.